p-channel enhancement mode power mosfet 08/02 /2007 rev.1.00 www.siliconstandard.com 1 SSM2307GN product summary simple drive requirement small package outline surface mount device description the advanced power mosfets from silicon standard corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the sot-23 package is universally preferred for all commercial- industrial surface mount applications and suited for low voltage applications such as dc/dc converters. absolute maximum ratings g d s d g s sot-23 bv dss -16v r ds(on) 60m i d - 4a symbol units v ds v v gs v i d @t a =25 a i d @t a =70 a i dm a p d @t a =25 w w/ t stg t j symbol value unit rthj-a thermal resistance junction-ambient 3 max. 90 /w rating -16 8 -4 0.01 1.38 -55 to 150 parameter drain-source voltage gate-source voltage continuous drain current 3 continuous drain current 3 -3.3 pulsed drain current 1 -12 parameter total power dissipation operating junction temperature range storage temperature range -55 to 150 linear derating factor t hermal data pb-free; rohs-compliant
0 8/02 /2007 rev.1.00 www.siliconstandard.com 2 SSM2307GN electrical characteristics (t j =25 o c unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -16 - - v b v dss / t j breakdown voltage temperature coefficient reference to 25 , i d =-1ma - -0.01 - v/ r ds(on) static drain-source on-resistance 2 v gs =-4.5v, i d =-4a - - 60 m v gs =-2.5v, i d =-3.0a - - 70 m v gs =-1.8v, i d =-2.0a - - 90 m v gs(th) gate threshold voltage v ds =v gs , i d =-250ua - - -1.0 v g fs forward transconductance v ds =-5v, i d =-4a - 12 - s i dss drain-source leakage current (t j =25 o c) v ds =-16v, v gs =0v - - -1 ua drain-source leakage current (t j =70 o c) v ds =-12v, v gs =0v - - -25 ua i gss gate-source leakage v gs =8v - - na q g total gate charge 2 i d =-4a - 15 24 nc q gs gate-source charge v ds =-12v - 1.3 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 4 - nc t d(on) turn-on delay time 2 v ds =-10v - 8 - ns t r rise time i d =-1a - 11 - ns t d(off) turn-off delay time r g =3.3 , v gs =-10v - 54 - ns t f fall time r d =10 -3 6 - ns c iss input capacitance v gs =0v - 985 1580 pf c oss output capacitance v ds =-15v - 180 - pf c rss reverse transfer capacitance f=1.0mhz - 160 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-1.2a, v gs =0v - - -1.2 v t rr reverse recovery time 2 i s =-4a, v gs =0v, - 39 - ns q rr reverse recovery charge di/dt=100a/s - 26 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 270 /w when mounted on min. copper pad. 100
0 8/02 /2007 rev.1.00 www.siliconstandard.com 3 SSM2307GN fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance v.s. gate voltage fig 4. normalized on-resistance v.s. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage v.s. reverse diode junction temperature 0 2 4 6 8 10 12 14 16 0123456 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a =25 o c v g = - 1.8 v -5.0v -4.5v -3.0v -2.5v 0 2 4 6 8 10 12 14 024 68 v ds , drain-to-source voltage (v) i d , drain current (a) t a = 150 o c v g = - 1.8 v -5.0v -4.5v -3.0v -2.5v 40 50 60 70 13 579 -v gs , gate-to-source voltage (v) r ds( on) ( ) i d =-3a t a =25 o c 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) norm alize d r ds( on) i d = - 4 a v g = -4.5v 0 1 2 3 0 0.2 0.4 0.6 0.8 1 -v sd , source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c 0.0 0.5 1.0 1.5 2.0 -50 0 50 100 150 t j , junction temperature ( o c) norm alize d - v gs( t h) (v)
0 8/02 /2007 rev.1.00 www.siliconstandard.com 4 SSM2307GN fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g -4.5v q gs q gd q g charge 0.01 0.10 1.00 10.00 100.00 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) t a =25 o c single pulse 1ms 10ms 100ms 1s dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) norm alize d th e rm al r e spon se ( r th ja ) 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse p dm duty factor = t/t peak t j = p dm x r thja + t a r thja = 270 /w t t 0 2 4 6 8 0 8 16 24 32 q g , total gate charge (nc) -v gs , gate to s o u r c e v oltage ( v ) i d =-4a v ds =-16v 100 1000 10000 15 9 1 3 1 7 -v ds , drain-to-source voltage (v) c (p f) f =1.0mhz c iss c oss c rss
SSM2307GN 0 8/02 /2007 rev.1.00 www.siliconstandard.com 5 information furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties.
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